1. Field of the Invention
Embodiments of the invention relate generally to semiconductor devices. More particularly, embodiments of the invention relate to semiconductor devices having a combination of low-voltage and high-voltage transistors and methods of manufacturing of these semiconductor devices.
This application claims priority to Korean Patent Application 10-2005-0127042, filed on Dec. 21, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Manufacturers of electronic goods are under constant pressure to supply devices having expanded functionality and lower prices. One example is the wireless cellular phone, where staunch competition between manufacturers and resellers has kept cellular phone prices down even as the range of cellular phone functionality has expanded dramatically. Indeed, cellular telephones now include such capabilities as e-mail, web-browsing, text-messaging, music storage, photography, and video playback.
In order to facilitate the trend towards expanded device functionality at lower prices, manufacturers must develop not only new processing architectures and algorithms, but also new semiconductor technologies allowing denser device integration at lower fabrication costs. However, increased device integration often requires a blending of heretofore incompatible technologies into a common device substrate.
Many contemporary electronic devices, such as cellular telephones, benefit from the inclusion of low-voltage (<3.3 VDC) CMOS devices (e.g., transistors) in the implementation of various circuitry (e.g., data encryption and decryption). However, the same electronic devices also benefit from the inclusion of relatively high-voltage (>5 VDC) devices in the implementation of other circuitry (e.g., modulators/demodulators and power amplifiers). Unfortunately, high-voltage devices do not generally function effectively at low-voltages, and the low-voltage devices can be damaged by high-voltages. These facts often resulted in the conventional provision of separate integrated circuits, one implemented in low voltage devices and another implemented in high voltage devices, within a host device. However, such an approach to dealing with the common provision of different types of devices are simple not possible under emerging pressures related to integration densities and fabrication costs.
To remedy this problem, a host of technical solutions has been developed. For example, a device known as an “asymmetric” metal-oxide-semiconductor (MOS) transistor has been proposed. In this type of MOS device, the drain region is substantially expanded in relation to a corresponding source region. With this structure, an asymmetric MOS transistor may be implemented within a predominantly low-voltage system, and yet operate at relatively high voltages without significant risk of damage.
FIG. 1 depicts an exemplary asymmetric MOS transistor 10 embedded between two shallow trench isolation (STI) structures 14. As shown in FIG. 1, asymmetric MOS transistor 10 is a p-channel MOS-type transistor having a gate 11 formed over a p-doped well 15. A source electrode 12 is connected to a heavily n-doped source region 17, and a drain electrode is connected to a heavily n-doped drain region 18. A lightly n-doped region surrounds heavily n-doped drain region 18.
The lightly n-doped well/region surrounding heavily n-doped drain region 18 imparts two properties to transistor 10. First, the effective channel length (LEFF) under gate 11 is reduced. Second, drain region 18 is effectively enlarged, which consequently gives asymmetric MOS transistor 10 a higher breakdown voltage (i.e., a greater ability to withstand higher applied voltages).
One particular example of an asymmetric MOS transistor is disclosed in U.S. Pat. No. 6,624,487, the subject matter of which is hereby incorporated by reference. A similar device is illustrated in FIG. 2.
In FIG. 2, a pair of asymmetric MOS transistors 32, 34 are provided in an electrostatic discharge (ESD) circuit. In first MOS transistor 32, a gate electrode 45 overlaps a portion of a lightly n-doped well 42 in which a heavily n-doped drain 44 is disposed. Similarly, for second MOS transistor 34, gate electrode 49 overlaps a portion of a lightly n-doped well 51 in which a heavily n-doped drain 48 is disposed. In the illustrated example, the drains of first and second MOS transistors 32, 34 are commonly connected to a terminal (not shown). Corresponding gates 45, 49 of respective first and second MOS transistors 32, 34 are also commonly connected. The deep drain-extended junctions, located at the interface between N-wells 42, 51 and substrate 40, provide a large junction area capable of handling a substantial current passing from substrate 40 to the above-mentioned terminal when forward-biased by a negative polarity ESD event.
While the asymmetric MOS transistors 32, 34 of FIG. 2 have proven useful for handling relatively high-voltages, they may suffer from an absence (or inadequate) of electrical isolation between one another, and between other proximate devices. To counter this electrical isolation problem, two additional structures are routinely included within substrates incorporating asymmetric MOS transistors adapted for use with relatively high applied voltages. These additional structures are sometimes referred to as “guard rings” and “triple wells”.
FIG. 3 conceptually illustrates the use and placement of guard rings 86 and a triple well 84 within a semiconductor device 70. The generalized semiconductor device 70 includes, for example, an n-channel transistor 82 and a p-channel transistor 80 separated, and surrounded by, a number of shallow trench isolation (STI) structures 74. In turn, STI structures 74 are separated by intermediate N-wells biased to VDD and intermediate P-wells biased to VSS. The consequential effect of STI structures 74 and intermittent N-wells and P-wells, which collectively form guard rings 86, is one of increased electrical isolation between transistors 80 and 82, as well as to other proximate devices.
Triple-well 84 is also illustrated in FIG. 3 and is disposed under an enlarged P-well region of transistor 82. Triple well 84 is typically formed from a lightly n-doped region adjacent to the enlarged P-well. As with guard rings 86, triple-well 84 substantially increases the electrical isolation of transistor 82 with respect to other devices proximately disposed on the substrate, and more particularly prevents current leakage from the P-well through the P-type substrate.
While guard rings and triple-wells may be used to effectively isolate asymmetric MOS devices on a substrate, their formation significantly complicates and increases the cost of the overall fabrication process. That is, the provision of guard rings and triple-wells consumes increasingly scarce substrate area, and requires the use of additional fabrication masks. Accordingly, new technology related to the cost effective fabrication and incorporation of asymmetric MOS devices within a substrate is highly desirable.